Solving the ESD challenges in SOI technology

Recently, advanced SOI technology nodes are being used more extensively due to a number of advantages mainly related to the reduction of the power consumption, smaller silicon area, shorter gate delay and reduced parasitic junction capacitance. Moreover, due to the completely isolated transistors, latch-up is no longer an issue. The main SOI players collaborate in the SOI Industry Consortium to promote the use of SOI technology.

However, SOI technology comes also with disadvantages such as the higher cost for the starting material and increased self-heating issues. Another main disadvantage is the fact that traditional ESD concepts have a much reduced (It2) failure current. This reduction compared to bulk CMOS is related to the thin silicon film and the complete isolation of the transistors which limits the dissipation and transfer of the generated heat. The MOS devices are very sensitive against ESD stress, not only for gate-to-source stress but also for drain-to-source stress. Even a forward diode, a key element for many ESD concepts, has a much lower robustness as compared to bulk CMOS.

In a seminar (Shanghai, September 2015) Sofics summarized the main ESD challenges in SOI technology and provided information about ESD concepts that have been successfully applied in SOI CMOS technology, including low resistive diodes with improved ESD-performance-per-area and self-protective MOS drivers through various layout concepts. Examples from several sources will be summarized. Finally, the presentation covers a patented layout method to create Silicon Controlled Rectifiers which can provide a very area efficient solution for many ESD challenges.

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More information related to SOI from Sofics:

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