An LCD driver manufacturer wanted to reduce its total product die size by 10% to regain cost competitiveness and market share. ESD robustness was not an issue, but die size (including ESD area) was a challenge.
Most of the manufacturer’s products achieved protection levels of 2kV HBM and 200V MM. A re-spin for ESD was required in only a limited number of cases. ESD protection was provided through a simple but effective dual diode plus power clamp approach, but even that consumed too much area.
Sofics studied the process and the application. We optimized the diode size and layout, reduced the I/O bus scheme and area, designed a new Sofics power clamp, and worked out a calculation sheet to determine optimum power clamp placement. This resulted in a 25% I/O size reduction, and an overall die area reduction of more than 12%, significantly cutting the product’s manufacturing cost.
Porting to the customer’s process and first product verification was completed within one silicon cycle, only 6 months from the start of the project. Immediately afterwards the first new LCD driver IC using the Sofics small area solution was released for mass production.
In addition to the die area reduction, our solution removed one mask and one step from the process, further reducing costs. It also established a design process for other ICs in the technology. Since the Sofics engagement the customer has been able to make consistently smaller I/O’s and power cells, and has reduced the power clamp repetition rate. These enhancements lead to smaller and hence cheaper product dies. The customer has been rewarded with significantly increased competitiveness and a bigger market share.