On-chip ESD protection for SerDes interfaces

Sofics TakeCharge

High speed digital interfaces are on the rise. Consumer as well as IoT applications create and demand a lot of data. Legacy interface protocols are upgraded to carry more data per second. Just think about USB, HDMI/DisplayPort or PCIe. All have different versions with ever increasing bandwidth. Also the infrastructure (e.g. server connections) needs to follow this trend. When copper connections are too slow they start using optical interconnects.

Clearly, the communication speed of integrated circuits is steadily going up. A few years ago 10Gbps was considered state-of-the-art. Nowadays companies are already developing 50Gbps interfaces.

To protect such high speed digital interfaces IC-designers against Electrostatic Discharge (ESD) there are a few challenges:

  • For the highest speed IC firms use the most advanced CMOS node (40nm, 28nm, 16nm). They tend to use the core transistors. The problem is that those transistors are extremely sensitive. Under ESD stress they fail around 4V or lower. Only a local protection concept is feasible.
  • To ensure signal integrity the ESD cells should have very low parasitic capacitance.
  • Some interfaces cannot tolerate a diode from pad to Vdd. The diode capacitance would ruin the on-chip termination resistance and causes CMRR reduction.

Several companies worldwide rely on the TakeCharge ESD protection clamps to protect high speed interfaces, LVDS, SerDes, TMDS… When generic or foundry on-chip protection against ESD do not meet your needs, TakeCharge® technology is the logical choice. Proven in thousands of ICs in commercial production, it offers a fast, reliable way to balance ESD protection with cost while enabling maximum IC performance.

Design without constraints

  • Protect interfaces with the most sensitive nodes like thin gates, core devices
  • Low parasitic capacitance for high speed circuits
    • 200fF, 100fF or lower
  • Enable high ESD protection when needed
    • HDMI, DisplayPort, USB: direct contact with end-user requires IEC 61000-4-2 protection

Reduce time to market by several months

  • ESD concepts with low parasitic capacitance available
    • TSMC: 180nm, 130nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm
    • UMC: 180nm, 130nm, 65nm, 28nm
    • GF: 65nm
    • SMIC: 40nm
    • Several other foundries like TowerJazz, HHGrace, …
  • Customized EOS/ESD solutions for other nodes or foundries can be delivered within a few days

Strongly reduce IC cost

  • Silicon and product proven ESD solutions help to reduce IC development costs
  • Compatible with standard process flow.
  • Optical interconnect projects with several key players in UK, US
  • High speed SerDes interfaces from companies worldwide use Sofics ultra-low cap. IP.


Does your next chip design also requires custom ESD solutions? Contact us at sofics.serdes@mob32.com