In 2006 Former Intel senior vice president Pat Gelsinger stated:
“Today, optics is a niche technology. Tomorrow, it’s the mainstream of every chip that we build.”
Indeed, optical interconnects are important for high speed communication inside and between data centers.
Recent projects only require external laser diodes since all other functions are integrated in a CMOS die. To enable high speed communication between the CMOS die and the laser diode the parasitic capacitance of the on-chip ESD (Electrostatic Discharge) protection should be as small as possible.
Several optical interconnect projects in the past 5 years rely on the TakeCharge ESD protection clamps. When generic or foundry on-chip protection against ESD do not meet your needs, TakeCharge® technology is the logical choice. Proven in thousands of ICs in commercial production, it offers a fast, reliable way to balance ESD protection with cost while enabling maximum IC performance.
Design without constraints
- Protect interfaces with the most sensitive nodes like thin gates, core devices
- Low parasitic capacitance for high speed circuits
- 200fF, 100fF or even below 15fF
Reduce time to market by several months
- ESD concepts with low parasitic capacitance available
- TSMC: 180nm down to 28nm
- UMC: 130nm, 65nm, 28nm
- GF: 65nm
- SMIC: 40nm
- Several other foundries, …
- Customized EOS/ESD solutions for other nodes or foundries can be delivered within a few days
Strongly reduce IC cost
- Silicon and product proven ESD solutions help to reduce IC development costs
- Compatible with standard process flow.
- Optical interconnect projects with several key players in UK, US
Does your next chip design also requires custom ESD solutions? Contact us at email@example.com