Low capacitance IO protection for FinFET technology

Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 28nm across various fabs and foundries and now also for the first time for FinFETs. The ESD clamp concepts are silicon and product proven in more than 3000 mass produced IC-products. The Sofics ESD clamps provide competitive advantage through improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.

The ESD clamp described below protects 0.8V IO interfaces in FinFET technology.

Sometimes it is required to use thin oxide, core transistors for high speed interfaces. E.g. designers that want to create a 30Gbps SerDes interfaces will need to use the 0.8V devices. Of course these devices are extremely sensitive and need adequate protection during ESD stress.

  • Due to the high speed it is not possible to include a resistor in the pad to use a so-called secondary protection concept.
  • In mature processes it was possible to create self-protective drivers but as shown in part 2, the core devices do not survive snapback operation.
  • The other typical approach, dual diode and rail clamp, is not possible because the ESD design window is too small. The voltage across diode, bus and power clamp easily exceeds that.
  • A feasible solution is to use a local protection clamp between pad and ground like shown below for a differential HDMI TMDS output.
  • HDMI_TMDS_ESD_protection

Clamp type and usage

The Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below. The ESD clamp cell described here is a type C clamp.

clamptypes

Stress cases covered

  • PAD to VSS
  • VSS to PAD
  • PAD to VDD
  • VDD to PAD

Features

  • Effective ESD protection
    • >2kV HBM
    • >2A TLP
  • Leakage (PAD to VSS, while VDD is biased)
    • 1nA at 125°C
  • Low parasitic junction capacitance
    • 100fF at PAD
  • Small silicon footprint
    • <2000um²

TLP plot

16nmFinFET_0V8_EON_Clamp_TLP16nmFinFET_0V8_EON_Clamp_Capacitance

 

Another example is the AO-clamp from Sofics (PAD to VSS stress shown).

16nmFinFET_0V8_AO_Clamp_TLP

If you are looking for another ESD protection in FinFETs or other technology please connect via email or browse the other examples.

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