ESD Protection For Real Time Location Systems

Despite the improved ESD awareness and control in assembly factories and the related push for a reduction of component level ESD performance, ICs still need adequate ESD protection. In many cases, traditional ESD protection devices used for low speed digital interfaces, such as those offered by foundries and IO library providers, are not suited for the RF interfaces for a number of reasons:

  • Capacitive loading shunts large part of the RF signal to VDD/VSS lines due to high parasitic junction and metal capacitance  of ESD clamps
  • Increased noise injected at the receiver due to series resistance used between primary and secondary ESD clamps
  • DC leakage current influences the size of the bias circuits

To reduce the cost of consumer electronics devices, designers also try to combine different standards into a single silicon die. This adds more constraints for the ESD protection approaches: the clamp parasitic influence should be as stable as possible across a large frequency band and voltage range.

This article describes the ESD protection solution used in a real time location system.

An SCR-based protection clamp is validated for a 8.5GHz LNA designed in TSMC90nm LP. The ESD protection is designed to protect the ultra-wideband RF circuits based on the IEEE 802.15.4a standard. This standard is an alternate PHY and adds location awareness, low power and higher data rates to the PHY and MAC specification for Zigbee devices. The circuit can be used for accurate real-time indoor location of resources/assets and in wireless sensors for health, retail, manufacturing and security sectors. One of the key requirements is the low leakage core and IO circuits. The chip operates off a single watch battery for up to 10 years.


The proprietary circuit to be protected consists of 3.3V transistors leading to a failure voltage (ESD design window) of 11.4V. This enables various ESD protection concepts but there are additional constraints.

  • To leave room for a large analog circuit including coils on the top metal, the IO ring is designed such that there is only a low resistive VSS bus available at the RF interfaces. This means that a ‘dual diode’ protection is not feasible. The connection to the VDD pad has too much resistance to shunt ESD current.
  • To enable the high frequency signals the parasitic capacitance of ESD clamps has to be below 100fF.
  • Further more the clamp leakage at room temperature must be below 1nA.


The selected protection design consists of an SCR clamp triggered by a NMOS device with dynamic gate bias. The layout includes the SCR clamp, NMOS trigger, RC ESD detection filter, reverse diode and all required guard bands within an area of 55.91um by 52.08um. Thanks to this small area the ESD cell could be located under the bond pad (Circuit Under Pad – CUP) leaving room for the large area inductors of the RF circuit. Besides the IO pad and a wide metal connection to VSS, a narrow connection to VDD is required to keep the capacitance of the RC detection circuit charged up during functional operation of the circuit. This way the diode from pad to anode stays reverse biased.

The parasitic capacitance loading of the ESD clamp is calculated based on available models from the foundry following the equivalent circuit consisting of 9 junction capacitances and 7 metal capacitance values. The total IO capacitance is less than 100fF.


The design guarantees effective ESD protection up to 2kV HBM, well above the standard requirement used for RF interfaces in advanced CMOS technology. This means that the chip can be handled in low cost assembly houses to push down the cost of the system.

Thanks to the low capacitive loading of ~99fF and low leakage below 0.1nA (@ 25°C), 55nA (@ 125°C) the clamp does not influence the RF behavior thereby greatly simplifying the design of the RF circuits.

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