ESD Protection of Bluetooth Interfaces

Nowadays, mobile consumer electronics devices integrate various wireless interfaces like WIFI, Bluetooth, GPRS and GPS. Several approaches exist to protect wireless interfaces against ESD stress. In recent years, researchers have focused on so-called ‘co-design’ techniques to solve both functional and protection constraints together. This requires both RF and ESD design skills.

However many IC designers still prefer to work with ‘plug-n-play’ protection concepts where the ESD clamps exhibit low parasitic capacitance, low series resistance and low leakage. In that way the RF/analog designers can focus on their expertise and then just add the ESD clamps during the physical layout.

This article provides information about the ‘plug-n-play’ ESD protection of a Bluetooth application.

Two different SCR (Silicon Controlled Rectifier) based protections approaches that exhibit high Q-factor and low stable parasitic capacitance over a broad voltage and frequency range are compared. The clamps are used for the protection of 1.1V wireless interfaces in a 40nm Low Power CMOS technology.

The variation between the clamps is mainly related to the trigger concept:

  • The ESD-on-SCR is triggered as soon as the IO level raises 1 diode drop (Anode-G2) above the VDD voltage. This never happens during normal functional operation.
  • The DTSCR (diode triggered SCR) is turned on once the Anode-G2 and 3 trigger diodes are forward biased. The trigger voltage is beyond the signal range in normal functional operation.

Besides these two main types some other variations were combined on an RF/ESD test chip to validate the SCR based protection for wireless circuits.


All SCR clamps were designed for 2kV HBM and 200V MM which corresponds to more than 2A of TLP current in the TSMC 40nm process technology. The SCR perimeter of 2x47um is the same for all devices. All of the devices use 4 layers of metal leaving all other metal layers for bus routing. To limit noise coupling, all devices described here use the Deep Nwell layer.

Each clamp type is connected to Ground-Signal-Ground pads to obtain accurate capacitance and Q-factor values. De-embedding structures (short, open) are available too.


ESD devices are available as stand-alone clamps (for accurate leakage tests) and with 2 different monitor structures to characterize the effectiveness of the ESD protection:

  • The ‘GOX’ monitor is a minimum size, fully-silicided thin oxide transistor with gate connected to the IO pad
  • The ‘RC-MOS’ monitor is a minimum size, fully-silicided thin oxide transistor where drain is connected to pad, source to ground and gate is biased at 1/3 of the drain voltage through an RC-filter scheme

To fully qualify the clamps, TLP measurements, stress testing, HBM/MM measurements, DC leakage measurements and S-parameter analysis have been done on the ESD clamps.

Below figure shows the TLP IV curves of the 2 devices. The clamping device (SCR) is the same in the 2 device types also evident from the figures: the clamping behavior is exactly the same. The failure current It2 is more than 2.5A. After subtracting a safety margin of about 20% to cover process variations the maximum current level (‘Imax’) is more than 2A for all devices. As expected, the triggering of the ESD-on-SCR is strongly different compared to the DTSCR and makes it more effective for protection of these sensitive circuits.


Besides standard TLP tests each clamp is also stressed with multiple pulses according to the same test setup. At least 1000 TLP pulses are applied at a fixed current level. The amplitude is fixed to the maximum current level ‘Imax’. The leakage current is measured after each set of 100 pulses. Failure is defined as any significant or systematic deviation from the pre-stress leakage current. All devices passed this test condition without leakage increase.

HBM and MM measurements were done as well.

  • The ESD-on-SCR passed 5.2kV HBM and 300V MM
  • The DTSCR passed 4.5kV HBM and 240V MM.

These are the minimum pass levels for HBM and MM, based on data of 6 samples (3 with ‘GOX’ monitor and 3 with ‘RC-MOS’ monitor)

The DC leakage measurements are performed on devices without a monitor device to accurately measure the clamp leakage. The measurements are performed on die at three temperatures: room temperature 25°C, 85°C and 125°C. The figure below shows that the intrinsic leakage of the ESD-on-SCR device is very low even in 40nm CMOS (~10 pA). The leakage of the DTSCR is determined by the diode trigger elements. The leakage stays below 100pA at room temperature when a diode chain is used to trigger the SCR.


Finally, the different clamps were measured with RF S-parameter equipment. After de-embedding based on ‘open’ and ‘short’ structures, the device parasitic capacitance (junction and metal combined) is determined as a function of IO bias voltage (between 0 and 1V) and frequency (between 1 and 20 GHz).


Besides these standard devices described above additional variations have been tested thoroughly including capacitance reduction circuits, SCR anode/cathode layout variations and versions without Deep Nwell. A summary of the ESD, Q-factor and capacitance values is given.


More information.