High speed SerDes interfaces integrated in Silicon Photonics products need adequate protection with minimal parasitic capacitance. This article introduces ESD clamps proven in 28nm CMOS for 28 to 56Gbps interfaces with record-low parasitic capacitance – respectively less than 15fF and 9fF.
Thanks to several breakthroughs during the last decade, optical communication has been transformed from a niche technology for long distances to a way to reduce cost/power and increase bandwidth for server-to-server interfaces within data centers.
The possibility to combine photonic elements and electrical dies in a single package through 2.5D or 3D hybrid integration enables low-cost mass-manufacturing. Hybrid integration allows designers to select the best process option for each function. The digital functions are designed in high end CMOS technology with high performance and small size. The photonic die however does not benefit from this minimum feature size and can thus be designed in a more mature SOI technology which significantly reduces the total cost.
The CMOS (electrical IC) is connected to the SOI optical substrate through solder bumps. The connection distance is very short ensuring low parasitic (R, L and C) effects. That is extremely important to enable high speed interfaces and to reduce power consumption of the interface.
Reliability constraints for the electrical die
To create high-speed differential circuits, IC-designers utilize thin oxide, low-voltage transistors. However, those transistors are very sensitive and can be easily damaged during transient events like Electrostatic Discharge (ESD). Despite the fact that the sensitive pads are not connected outside of the package, they can be exposed to ESD stress during assembly. Therefore, adequate protection clamps need to be inserted. The SOI photonic elements also need protection but that is not part of this work.
ESD analysis of advanced 28nm CMOS
This paper summarizes the results of 2 recent Silicon Photonic projects where the electrical die is manufactured in TSMC 28nm CMOS. While this process technology enables high speed digital interfaces it needs protection clamps to shunt the excess current to ground during ESD events. The 0.9V, thin oxide transistors in 28nm CMOS can be damaged during short transients. The maximum voltage is about 4V, as shown below.
During ESD the protection cell must shunt the stress current while clamping the voltage below this critical level. The maximum voltage in 28nm for low voltage transistors under ESD stress between drain and source is actually similar (4.5V).
In both projects, the focus has been on the protection of the low voltage domains with sensitive thin oxide transistors and the protection of the high-speed circuits (Tx, Rx – 28-56Gbps). Such interfaces are typically designed as differential circuits, simplified below.
Parasitic capacitance and resistance
Many advanced CMOS foundries provide a set of I/O and ESD protection circuits that designers can use. However, these standard, general purpose, interface blocks are not suitable for the Silicon Photonic designs.
- To ensure that the signals are not influenced it is important that the resistance in the path is as low as possible. Several protection concepts include an ESD isolation resistance and cannot be used for protection of these high-speed interfaces.
- The ESD clamp elements always introduce parasitic capacitance and leakage current. For signal integrity, it is important to limit this as much as possible. For the two projects in this article, the total capacitance from ESD must be below 20fF, which is a fraction of the typical capacitance level (150fF) of the analog I/O cells included in the free libraries.
- The SerDes interfaces typically operate at a voltage level below the standard I/O voltage levels (1.0V compared to 1.8V, 2.5V or 3.3V for I/Os).
For these products, two proprietary ESD-on-SCR clamps are used: one between I/O Pad and Vss and another for stress from Vdd to Pad. In one project, the local clamp also included a power protection clamp as depicted in the figure (right side).
ESD-on-SCR protection clamp
The ESD-on-SCR is an ESD circuit using a Silicon Controlled Rectifier or thyristor, depicted in the figure below. For the bottom clamp (figure above) for instance, the G2 (Nwell) node is connected to Vdd. During normal, functional operation the Nwell remains high and thus the device remains in a high impedance state (off). It is triggered, during ESD stress, as soon as IO level raises 1 diode drop (Anode-G2) above the Vdd voltage. It is a perfect ESD concept to protect sensitive transistor circuits because the turn-on voltage is very low.
1.0V SerDes protection in 28nm CMOS
In a first project on TSMC 28nm CMOS the 1.0V SerDes interface was designed using sensitive 0.9V transistors. Thanks to the hybrid integration the SerDes pads are not exposed outside of the semiconductor package. The required ESD protection level was reduced to 200V HBM.
The full local protection introduces a parasitic capacitance of less than 15fF, shown below. Thanks to the reduced HBM requirement the total size of the ESD clamp is also small, less than 700um². The leakage current at 1V is about 10pA at room temperature. The datasheet is available online.
Further reduction of the capacitance
In a second project, the capacitance level had to be further reduced. Fortunately, the required HBM level was also reduced to 100V.
Silicon Photonics can enable a strong growth of the (optical) communication market. Thanks to the mass production opportunity of both the optical and electrical dies and the availability of 2.5D and 3D hybrid integration all the requirements can be met: lower power, lower cost, high volume, high bandwidth.
High speed SerDes interfaces integrated in Silicon Photonics products need adequate protection with minimal parasitic capacitance. In this article, we demonstrated ESD protection clamps for 28 to 56Gbps interfaces in TSMC 28nm. Record-low parasitic capacitance levels of 9fF and 15fF were achieved.
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