Sofics recently had the opportunity to characterize a FinFET technology through cooperation with one of its customers. We analyzed the technology related to ESD. The following subsections summarize the challenges for on-chip ESD protection.
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Advanced circuits fail easily during ESD stress
The maximum allowed voltage on core circuits continues to drop. We analyzed simple gate oxide, junction or core victim circuits to extract the maximum allowed voltage.
Traditional ESD solutions run out of steam
In mature and mainstream technology nodes ESD protection is rather straightforward. Several options exist for core and local protection.
We analyzed the NMOS and PMOS devices into snapback operation and also so-called BIGfet circuits or rail clamps where a large NMOS is actively biased only during ESD events. Several detection and gate-bias-circuits were compared.
Thanks to the transistor scaling the total silicon footprint is reasonably small.
We also analyzed Nwell and Pwell diodes. Diodes in advanced technology show a reduced ESD performance and higher resistivity compared to mainstream technology. The achievable level is about the same as in 28nm CMOS.
Though metallization constraints
Typical advanced CMOS nodes provide 2 or 3 distinct groups of metallization. The local metals are getting thinner at every new node to allow narrower transistor pitch.
Increased design complexity
There is a significant increase in the number of design rules in FinFET technology. Several EDA vendors already pointed out that verifying FinFET-based circuits requires a computer system with several CPU-cores and a lot of DRAM memory. We also noticed a strong increase in ESD design complexity.