Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 28nm across various fabs and foundries and now also for the first time in the 16 FinFET technology. The ESD clamp concepts are silicon and product proven in more than 3000 mass produced IC-products. The Sofics ESD clamps provide competitive advantage through improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB
3.0, SATA, WIFI, GPS and Bluetooth.
The ESD clamp described below protects 5V interfaces.
Sofics frequently receives requests for 5V compatible ESD protection in advanced CMOS. There are several reasons for such 5V pins like legacy interface compatibility, battery supply, sensor interfaces, hot swap or fail safe interfaces. A simple dual diode based protection with 1.8 or 3.V supply reference is not possible in those cases. Therefore we included a number of 5V capable concepts on FinFET tape out. The example below is based on the N-SMOS concept.
Clamp type and usage
The Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below. The ESD clamp cell described here is a type B clamp.
Stress cases covered
- PAD to VSS
- VSS to PAD
- Effective ESD protection
- >2kV HBM
- >2.4A TLP
- Low Leakage, even at high temperature
- 30nA at 25°C
- Latch-up safe
- DC holding voltage above 5.5V