2016-2017 Master thesis UGent

Supervisor: Prof. B. Bakeroot
Tutors: Prof. B. Bakeroot (CMST) & O.Marichal (Sofics)

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Background

Whoever has experienced a spark between her/his fingertip and a doorknob knows that quite some voltage (over 10kV) and energy is involved. Imagine what the effect of such a spark on the IC of your smartphone or the IC controlling the breaks of your car could be… Due to the ever ongoing miniaturization of integrated circuits, a voltage of less than 5V can sometimes already cause a failure. In order to avoid damage, all IC’s have a built-in protection circuit against these hazards: ESD clamps (electrostatic discharge clamps).

Nowadays, IC’s are present in a multitude of devices, where they should be able to cope with very high power levels. This requires specialized processes which not always facilitate easy design of an adapted clamp.

IEC61000_4_2_zap

Goal

Due to the complexity of high power electronics, the failure mechanisms which are present are not always decently understood. Through measurements of specific devices which have been put on chip, the student investigates these mechanisms. Afterwards (s)he uses this information to redesign an IC so that it can withstand a specific level of electrostatic discharge. The student can choose to simulate the on-chip devices by means of Technology Computer Aided Design (TCAD or finite element numerical analysis) simulations. As a start, a simulation model which has been developed during a Master thesis of the previous year can be used.  Of course, the student would be assisted by CMST, where a long-standing experience is present on the field of TCAD simulations for (integrated) power devices. This thesis is in collaboration with the company Sofics, world leader in on-chip ESD protection.

This thesis gives the student a unique view on high power electronics exploring the limits of technology, which – in combination with the indispensable knowledge of the physics of semiconductor devices – leads to a true challenge both in the understanding of the physics as well as for the engineering aspect of designing improved ESD clamps.

Location

  • Technologiepark 914A Zwijnaarde (CMST)
  • Groendreef 31 Aalter (Sofics)

Key words

  • ESD, IC design, high power electronics, physics of semiconductor devices, cluster electronics, TCAD

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