1.8V IO protection in FinFET technology

Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 28nm across various fabs and foundries and now also for the first time on FinFET technology. The ESD clamp concepts are silicon and product proven in more than 3000 mass produced IC-products. The Sofics ESD clamps provide competitive advantage through improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.

The ESD clamp described below protects 1.8V IO interfaces in FinFET technology.

Clamp type and usage

The Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below. The ESD clamp cell described here is a type B clamp.


Stress cases covered

  • PAD to VSS
  • VSS to PAD

Other stress cases

  • VDD to PAD: Through separate power clamp (VDD-VSS) + diode (VSS-PAD) inside the cell
  • PAD to VDD: Through the local clamp inside the cell (PAD-VSS) + diode (VSS-VDD) in the power clamp cell.


  • Effective ESD protection
    • >2kV HBM
    • >2A TLP
  • Small silicon footprint
    • <1000um²

TLP plot



If you are looking for another ESD protection in FinFET or other technology please connect via email or browse the other examples.