0.8V core protection in FinFET technology

Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 28nm across various fabs and foundries and now also for the first time for FinFET+ technology. The ESD clamp concepts are silicon and product proven in more than 3000 mass produced IC-products. The Sofics ESD clamps provide competitive advantage through improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.

The ESD clamp described below protects 0.8V core domains.

Clamp type and usage

The Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below. The ESD clamp cell described here is a power clamp.


Stress cases covered

  • VDD to VSS
  • VSS to VDD


  • Effective ESD protection
    • >2kV HBM
    • >1.9A TLP
  • Low Leakage, even at high temperature
    • <10nA at 125°C
  • Small silicon footprint
    • <1000um²

TLP plot


If you are looking for another ESD protection please connect via email or browse the other examples.